Data-Over-Cable Service Interface Specifications (“DOCSIS”) has been established by cable television network operators to facilitate transporting data traffic, primarily internet traffic, over existing community antenna television (“CATV”) networks. In addition to transporting data traffic as well as television content signals over a CATV network, multiple services operators (“MSO”) also use their CATV network infrastructure for carrying voice, video on demand (“VoD”) and video conferencing traffic signals, among other types.
DOCSIS signals are transmitted over the CATV networks, which may be coaxial networks, fiber networks, or a combination of both known as hybrid fiber-coaxial networks (“HFC”). MSOs typically provide DOCSIS service to subscribers' cable modems (“CM”) from a cable modem termination system (“CMTS”) located at the MSOs head end facility. In providing connectivity to a plurality of subscribers, multiple subscribers connect to multiple circuit cards in the CMTS. Each of these circuit cards contains analog and digital circuitry for transmitting and receiving signals up to approximately 750 MHz.
For a variety of reasons, including load balancing, for example, the channel frequency to which a CM and CMTS use for communication may be changed. Often when a change is made, the CMTS uses a different card for communicating via the new frequency. Since the frequency is high, and the operation at such frequencies depends on a stable clock frequency, a connection may be lost when changing from one card to another if the respective clocks on the old and new cards are not in phase within a given tolerance. This tolerance is typically approximately 1 nS. As known in the art, phase detection/correction circuits may use a detector and an A/D converter to generate and provide a signal to a clock to cause it to shift, thus aligning it with another clock.
To achieve a 1 nS resolution, a 24 bit A/D converter would be needed to detect such a small offset over a 10 mS clock, for example. However, in a 3V system, a noise signal of just 180 pV could induce error into the phase detection process, thereby causing a shift of too much or too little. In addition, a 24 bit A/D converter is typically more costly and complex than one that provides lower resolution conversions, such as 8 or 10 bit converters.
Thus, there is a need in the art for a method and system for phase-aligning multiple clocks with a reference that provides adequate resolution and that is resistant to noise-induced error.